Hi! Welcome to our blog
Hi! Welcome to our blog
Here we share different ideas, designs, and implementations of various hardware blocks. Â
Here we share different ideas, designs, and implementations of various hardware blocks. Â
Implemented a 16-bit custom RISC ISA architecture with a 2-way set associative Cache memory using Verilog HDL. Testing is performed on FPGA board. Additionally wrote a Python Assembler for the ISA and implemented MNIST digit classification on the processor.
Best Paper Award at IEEE International Conference on Consumer Electronics (ICCE) 2020, Las Vegas, USA.
Paper link: ML_localization_autonomous_vehicle
Design and verification of synchronous FIFO using SystemVerilog Assertions (SVAs). Formal verification using open-source SymbiYosys tools. Final synthesis on FPGA board