RTL Design Practice Problems

Presenting my collection of 25 RTL design problems that I used to practice and improve my RTL skills. These are what I review, especially during my interview preparation process. They cover all the fundamentals required to design complex systems.

For a good grasp of digital implementation, one should be able to understand these designs at the clock cycle level. Also, note these designs will assume a good understanding of timing, synthesis, and SystemVerilog. If you are confident in writing good RTL and know what circuit will get synthesized for your RTL, these design problems will provide some fun practice. You should write the RTL and a testbench to ensure the specifications are met. Further, feel free to assume any additional signals as part of the design. I highly encourage using SystemVerilog Assertions in testbenches to stress test the designs.

Of course, I do not include my solution to them as that defeats the purpose of practice. So be brave and spend weeks or more to get through them as that will help improve the skills and fundamentals.

1. RTL for a fixed priority arbiter with decreasing priority from LSB to MSB.

2. RTL for a fixed priority arbiter with decreasing priority from MSB to LSB.

3. Implement a Round-Robin Arbiter with 3 I/p requests.

4. RTL Design synchronous FIFO buffer for generic depth.

5. Improve FIFO for high speed - registered flags, registered read (what additional logic will be needed to make sure we can still write and read to same address in consecutive cycles)

6. Micro-architect Reorder-buffer (ROB) and write RTL for it. 

7. RTL and circuit for a pulse synchronization circuit.

8. FSM design of a divisible 3 ( or 5) logic for serial input. Assume input goes to the LSB of the previously seen number.

9. Asynchronous FIFO implementation details.

10. RTL for binary to gray and gray to binary logic.

11. Implement NAND, XOR, and NOT gate using 2-to-1 MUX.

12. Implement 4-to-1 MUX using 2-to-1 MUXs.

13. RTL Design for an LRU cache replacement policy, consider a 4-way cache.

14. RTL for a 3-input sorting logic.

15. RTL for three input Median circuit

16. RTL for Fibonacci and Factorial algorithm.

17. Design clock divider logic for divide by 2,3,4,5.

18. RTL ready-valid downsizer. 16-bit input with ready/valid gets sent at output 1-byte at a time. Both I/p and O/P use ready/valid

19. Datapath components for a typical 4/5  stage CPU pipeline.

20. 11011 sequence detector FSM.

21. RTL for a) the index of the first set bit in 32-bit input. b) Number of 1’s in 32-bit input signal. 

22. Grayscale (average) conversion circuit without using division hardware. (inputs are 8-bit wide for the three channels)

23. Clock divide by 10 with a duty cycle of 40

24. SVAs for synchronous FIFO – as many as possible.

25. Using UART timing diagram, implement RTL for TX interface.