Silicon Hardware Design

Here, I present many different ASIC/RTL based projects that I have done as part of my personal projects. They cover design and verification strategies for full system design and verification. I am sharing these as tutorials and design projects for any new hardware designers looking for more learning opportunities.

There are many different FPGA/ASIC related good blogs out there, but they fail to provide a good explanation for designers just getting started. For software, design and debugging resources are easily available online but we lack good hardware design resources.

We design RTL using hardware description languages (HDLs). In particular, I will use SystemVerilog (SV) for both Design and Verification. There's a reason all design in the industry is now fully switched to SV due to many new language features it can provide (especially for writing complex testbenches). Writing about design and including code can create more confusion. I will be using the necessary code snippets in the blog description and will provide a GitHub link for full access to the RTL code.

Below are the different design projects/tutorials that I plan to cover.

• RTL practice design problems

• RTL design: 3-bit rules

• Ready/Valid buffered handshake

• Formal Verification using SystemVerilog

• Synchronous FIFO with generic depth

• Formal Verification Tutorial with Yosys Suite

• Finite State Machines

• Classes and OOP for design verification

• CPU design and ISA

• and many more . . .